Stereo Vision IP Core supports Zynq UltraScale+
With the Zynq UltraScale+, Xilinx has introduced a new generation of SoCs with integrated FPGA and ARM CPUs. Compared to the previous Zynq-7000 product line, the Zynq UltraScale+ SoCs are available with significantly more capable FPGAs and faster CPUs. The increase in FPGA resources can be used for accelerating computations, through additional parallelism. Our own stereo vision IP core, which drives our SP1 stereo vision system, can be easily configured to make use of the additional resources, for even more efficient image processing. For us it is thus consequential that we are among the first to support this new chip generation.
Today we have released a new version of the stereo vision IP core, which now officially supports the Zynq UltraScale+ product line. Little modifications were necessary to our image processing code in order to exhaust the full potential of these new devices. However, we had to make major modifications to the interfaces, in order to allow an easy integration with the Zynq's processing system. The new Zynq generation has switched form the AXI3 to the AXI4 protocol for memory accesses, which allows significantly larger burst sizes and lengths. Also, memory addresses have increased from 32 to 49 bits. All these changes are now available in our updated IP core, which also continues to support the previous Zynq-7000 generation.
Please consult the updated data sheet for further details on all changes.