Stereo Vision IP Core for FPGAs
The stereo vision IP core for FPGAs is what drives our SceneScan stereo vision sensor. If you require stereo vision capabilities for your own FPGA-based products, you can now license our IP core.
The stereo vision IP core performs stereo matching on two grayscale input images. The images are first rectified inside the FPGA to compensate for lens distortions and camera alignment errors. Stereo matching is then performed by applying a variation of the Semi Global Matching (SGM) algorithm, which has been optimezed for FPGA-based processing. Various post-processing methods are applied to improve the computed depth data. The output of the stereo vision core is a subpixel accurate and dense disparity map (an inverse depth map), which is streamed over an AXI4-Stream interface.
To simplify use of the stereo vision core on devices with a shared system memory, such as the Xilinx Zynq and Zynq UltraScal+ SoCs, an auxiliary core for direct memory access (DMA) is provided. This DMA core reads input data from memory through AXI3, and converts it into a data stream that is suitable for the stereo vision core. Likewise, the DMA core collects the processing results from the stereo vision core and writes them back to memory.
If you are interested in licensing our FPGA IP cores then please contact us.
- General processing architecture
- Processing of grayscale images with a bit depth of 8 or 12 bits per pixel
- Stream-based processing of input images using either AXI4-Stream, AXI4 or AXI3
- Configuration through AXI4-Lite interface
- Output of disparity map starts before receiving the last pixel of both input images
- Support for variable image sizes
- Multi-clock design with faster clock for performance critical tasks
- Image rectification
- Rectification using a pre-computed compressed rectification map
- Bi-linear interpolation for subpixel accurate rectification
- Stereo matching
- Stereo matching through a variation of the Semi-Global Matching (SGM) algorithm
- Configurable disparity range form 32 to 256 pixels
- Configurable disparity offset
- Configurable penalties P1 and P2 for small and large disparity variations
- Pre-processing of input images for improved robustness against illumination variations and occlusions
- Subpixel optimization
- Consistency check with configurable threshold
- Uniqueness check with configurable threshold
- Filling of small gaps through interpolation
- Noise reduction
- Speckle filtering
- Filtering of untextured image areas